1. Field of the invention
The present invention relates to a debugging microprocessor used in a microprocessor development support system, and more specifically to a debugging microprocessor having a generator for generating a bus cycle end signal for a microprocessor development support system having a function capable of tracing and analyzing the result of execution.
2. Description of related art
Hitherto, two types of debugging microprocessors have been known. A first type of debugging microprocessor is such that the sampling timing of a ready signal is different from the sampling timing of data, and therefore, data is sampled at a clock state next to a clock state in which the ready signal is rendered effective. Further, this type of debugging microprocessor is constructed to generate a bus cycle signal BCY indicative of a bus cycle and a data strobe signal DS for input/output of data. Therefore, the bus cycle signal BCY or the data strobe signal DS is added, as the content to be traced, to an address, data and the like, and then, the bus cycle signal BCY or the data strobe signal DS being traced is checked so that effective address and data contained in the content being traced are clarified, with the result that it is possible to analyze an executed instruction on the basis of the trace result. Accordingly, a microprocessor development support system in combination with this type of debugging microprocessor will involve no problem in the analysis of the trace result.
A second type of debugging microprocessor is such that the sampling timing of a ready signal is the same as the sampling timing of data, and therefore, data is sampled at the same time as the ready signal is judged to be effective. The latest high performance microprocessors are of this type, and therefore, recent debugging microprocessors are also of this type.
The second type of debugging microprocessor is constructed to output a bus cycle start signal BST indicative of the start of the bus cycle, but does not generate a signal corresponding to the bus cycle signal BCY or the data strobe signal DS of the first type of debugging microprocessor. Namely, since there is no signal corresponding to the bus cycle signal BCY or the data strobe signal DS, effective input data is not certain. Therefore, the microprocessor development support system using this type of debugging microprocessor has been required to trace the ready signal READY for the purpose of detecting effective input data.
As mentioned above, since the second type of debugging processor is adapted to generate the bus cycle start signal, it is possible to detect the time when an address is effective, by tracing the bus cycle start signal. On the other hand, in order to detect the time when the input data is effective, it is necessary to trace the ready signal. Furthermore, there is no way other than to conclude that the data appearing when the ready signal being traced is in an active condition is effective. However, even if the ready signal being traced is in an active condition, it may happen that the debugging microprocessor itself does not judge that the ready signal at this time is active. Namely, sufficient reliability cannot be obtained in detecting correct effective input data on the basis of the trace data.